Saturday, February 17, 2018

Materials of 3rd Workshop on Image Sensor and Systems Published

Image Sensor Society web site published most of the papers from 3rd International Workshop on Image Sensor and Systems (IWISS2016) held at the Tokyo Institute of Technology in November 2016. There are 18 invited papers and 20 posters presented at the Workshop, mostly from Japan and Korea.

Thanks to NT for the pointer!

Friday, February 16, 2018

LIN-LOG Pixel with CDS

MDPI Special Issue on the 2017 International Image Sensor Workshop publishes NIT paper "QLog Solar-Cell Mode Photodiode Logarithmic CMOS Pixel Using Charge Compression and Readout" by Yang Ni.

"In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light conditions and logarithmic response in high light conditions. The charge transfer readout efficiently suppresses the reset (KTC) noise by using true correlated double sampling (CDS) in low light conditions. In high light conditions, thanks to charge domain logarithmic compression, it has been demonstrated that 3000 electrons should be enough to cover a 120 dB dynamic range with a mobile phone camera-like signal-to-noise ratio (SNR) over the whole dynamic range. This low electron count permits the use of ultra-small floating diffusion capacitance (sub-fF) without charge overflow. The resulting large conversion gain permits a single photon detection capability with a wide dynamic range without a complex sensor/system design. A first prototype sensor with 320 × 240 pixels has been implemented to validate this charge domain logarithmic pixel concept and modeling. The first experimental results validate the logarithmic charge compression theory and the low readout noise due to the charge-transfer-based readout."


"The readout noise was measured at 2.2 LSB, which is 268 µV. Taking into account the source follower gain, the temporal noise on the floating diffusion was estimated at 335 µV. With a floating diffusion node capacitance estimated from design at 4 fF, the noise electron number is 12.3 electrons. The temporal noise in the logarithmic regime was measured at 6 LSB, which represents 34 electrons inside the buried photodiode. From this Johnson noise, the photodiode capacitance can be estimated at 6.2 fF which is quite close to the estimation from the layout."

Thursday, February 15, 2018

DALSA Discusses Facial Recognition

Teledyne DALSA starts publishing a series of articles on facial recognition science. The first part discusses fairly generic issues, such as the resolution that humans use for facial recognition task. It's all dynamic:

"The ganglion cells in the human retina can produce the equivalent of a 600 megapixel image, but the nerve that connects to the retina can only transmit about one megapixel."

"Analysts predict that the global facial recognition market is expected to grow from USD 4.05 Billion in 2017 to USD 7.76 Billion by 2022. Companies are very interested in the possibilities of facial recognition technologies and global security concerns are driving interest in better biometric systems."

ISSCC Review: Sony, TSMC, NHK, Toshiba, Microsoft, TU Delft, FBK

Albert Theuwissen continues his review of ISSCC 2018 presentations. The second part includes Sony 3.9MP, 1.5um pixel pitch event-driven sensor:

"The overall resolution of 3.9 Mpixels is reduced to on 16×5 macro pixels. In this “macro” pixel mode, the power consumption is drastically reduced as well, and the sensor behaves in a sort of sleeping mode. Once the sensor detects any motion in the image (by means of frame differencing), the device wakes up and switches to the full resolution mode."

TSMC presents their 13.5MP 1.1um pixel sensor and NHK unveils 8K 36MP 480fps sensor for slow-mo sports shooting at the oncoming Tokyo Olympics.

The third part of the review starts with Toshiba hybrid LiDAR that is enhanced by a Smart Accumulation Mode that, basically, tracks the subjects in depth domain. As long as it works, the detection range can reach 200m, but it relies on a lot of intelligence inside what is supposed to be just a dumb sensor delivering the "food for thought" to the main CPU or NPU.

Microsoft presented an evolution of its ToF sensor used in Kinect-2 - higher resolution, smaller pixels, BSI, higher QE, better shutter efficiency, etc. AGC has been added to the pixel, and background light suppression has been removed, if we compare this pixel with the previous Microsoft design.

TU Delft and FBK presented SPAD designs. The FBK one is aimed to entangled photon microscopy to increase the resolution by a factor of N, where N is the number of mutually entangled photons.

Albert Theuwissen concludes his review on an optimistic note:

"Take away message : everything goes faster, lower supply voltages, lower power consumption, stacking is becoming the key technology, and apparently, the end of the developments in our field is not yet near ! The future looks bright for the imaging engineers !!!"

Panasonic 8K GS OPF Sensor

Panasonic has developed an 8K (36MP), 60fps, 450ke- saturation sensor with global shutter and with sensitivity modulation function. The new CMOS sensor has an organic photoconductive film (OPF).

"By utilizing this OPF CMOS image sensor's unique structure, we have been able to newly develop and incorporate high-speed noise cancellation technology and high saturation technology in the circuit part. And, by using this OPF CMOS image sensor's unique sensitivity control function to vary the voltage applied to the OPF, we realize global shutter function. The technology that simultaneously achieves these performances is the industry's first."

The new technology has the following advantages:
  • 8K resolution, 60fps framerate, 450Ke- saturation and GS function are realized simultaneously.
  • Switching between high sensitivity mode and high saturation mode is possible using gain switching function.
  • The ND filter function can be realized steplessly by controlling the voltage applied to the OPF.

This Development is based on the following technologies:
  1. "OPF CMOS image sensor design technology", in that, the photoelectric-conversion part and the circuit part can be designed independently.
  2. "In-pixel capacitive coupled noise cancellation technique" which can suppress pixel reset noise at high speed even at high resolution
  3. "In-pixel gain switching technology" that can achieve high saturation characteristics
  4. "Voltage controlled sensitivity modulation technology" that can adjust the sensitivity by changing the voltage applied to the OPF.

Panasonic holds 135 Japanese patents and 83 overseas patents (including pending) related to this technology.

Wednesday, February 14, 2018

Analyst: Himax/Qualcomm 3D Sensing Platform Struggles in China

Barron's quotes financial analyst Jun Zhang of Rosenblat saying:

"As we look across the landscape it appears to us that HIMX continues to struggle to find OEMs to incorporate its solution as our latest industry research suggests OPPO is working with Orbbec, Xiaomi with O-film (002456-SZ:NR) & Mantis Vision for its Mi7 Plus and Huawei on an internal solution. We also be- lieve other tier-2 and 3 OEMs are targeting a 2019 launch for their phones. On the conference call, management commented that its 3D sensing solution will be ready for mass production in Q2 but did not announce any design wins. Based on the long lead times for 3D sensing modules, Himax should have needed to have already secured a design-win if to be part of any solution."

SeekingAlpha earnings call transcript has the company's CEO Jordan Wu predicting: "3D sensing will be our biggest long term growth engine and, for 2018, a major contributor to both revenue and profits, consequently creating a more favorable product mix for Himax starting the second half of 2018."

Teledyne Announces Readiness of Wafer Level Packaged IR Sensors

BusinessWire: Teledyne DALSA completed the qual of a its Wafer-Level-Packaged Vanadium Oxide (VOx) Microbolometer process for LWIR imaging.

Teledyne DALSA’s manufacturing process, located in its MEMS foundry in Bromont, Quebec, bonds two 200 mm wafers precisely and under high vacuum, forming an extremely compact 3D stack. This technology eliminates the need for conventional chip packaging - which can account for 75% or more of the overall device cost.

This is an important milestone in our journey to bring a credible price/performance VOx solution to market,” said Robert Mehrabian, Chairman, President and CEO of Teledyne. “With the qualification process complete we will now begin ramping up production lines for a 17-micron pixel 320×240 (QVGA) device, closely followed by a 17-micron 640×480 (VGA), with longer-term plans to introduce a highly compact 12-micron detector family.

ISSCC 2018 Review - Sony, Panasonic, Samsung

Albert Theuwissen publishes a review of ISSCC papers, starting from Sony BSI-GS CMOS imager with pixel-parallel 14b ADC: "One can make a global shutter in a CMOS sensor in the charge domain, in the voltage domain, but also in the digital domain. The latter requires an ADC per pixel (also known as DPS : digital pixel sensor). And this paper describes such a solution : a stacked image sensor with per pixel a single ADC."

Panasonic organic sensor: "The paper claims that the reset noise is lowered by a factor of 10, while the saturation level is increased by a factor of 10 (but the high saturation mode cannot be combined with the low noise level)."

Samsung 24MP CIS with 0.9um pixel: "All techniques mentioned are not new, but their combination for a 0.9 um is new."

Omnivision HDR Promotional Video

Omnivision publishes HDR marketing video:

Update: Omnivision removed the video and sent me the following update:

"The video was made public by mistake. Once we finalize the video we will re-publish and share with OmniVision’s customers and media contacts."

Tuesday, February 13, 2018

Sony Presents GS Sensor with ADC per Pixel

Sony presents 1.46MP stacked BSI CMOS sensor with Global Shutter and newly developed low power pixel-parallel ADC to convert the analog signal from all pixels, simultaneously exposed, to a digital signal in parallel.

The inclusion of nearly 1,000 times as many ADCs compared to the traditional column-parallel ADC architecture means an increased demand for current. Sony addressed this issue by developing a compact 14-bit A/D converter which is said to boast the industry's best performance in low-current operation. The FoM of the new ADC is 0.24e-・nJ/step. (power consumption x noise) / {no. of pixels x frame speed x 2^(ADC resolution)}.

The connection between each pixel on the top chip uses Cu-Cu connection, that Sony put into mass production as a world-first in January 2016.

Main Features:
  • Low-current, compact pixel-parallel A/D converter
    In order to curtail power consumption, the new converter uses comparators that operate with subthreshold currents, resulting in the low current, compact 14-bit ADC. This overcomes the issue of the increased demand for current due to the inclusion of nearly 1,000 times as many ADCs in comparison with the traditional column ADC.
  • Cu-Cu (copper-copper) connection
    To achieve the parallel A/D conversion for all pixels, Sony has developed a technology which makes it possible to include approximately three million Cu-Cu (copper-copper) connections in one sensor. The Cu-Cu connection provides electrical continuity between the pixel and logic substrate, while securing space for implementing as many as 1.46 million A/D converters, the same number as the effective megapixels, as well as the digital memory.
  • High-speed data transfer construction
    Sony has developed a new readout circuit to support the massively parallel digital signal transfer required in the A/D conversion process using 1.46 million A/D converters, making it possible to read and write all the pixel signals at high speed.